![Figure 6 from Hardware / Software Co-Design using LEON3 Processor: AES as Case Study | Semantic Scholar Figure 6 from Hardware / Software Co-Design using LEON3 Processor: AES as Case Study | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/1aa8c7269b86c76baf81fee193f333a7ad1dc160/2-Figure2-1.png)
Figure 6 from Hardware / Software Co-Design using LEON3 Processor: AES as Case Study | Semantic Scholar
GitHub - hdantas/leon3-processor: Rewriting the Multiplier and Divider to improve LEON3's core performance.
![PPT - FPGA Design Using the LEON3 Fault Tolerant Processor Core PowerPoint Presentation - ID:3221746 PPT - FPGA Design Using the LEON3 Fault Tolerant Processor Core PowerPoint Presentation - ID:3221746](https://image1.slideserve.com/3221746/leon3-sparc-v8-processor-cont-l.jpg)
PPT - FPGA Design Using the LEON3 Fault Tolerant Processor Core PowerPoint Presentation - ID:3221746
![Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design - ScienceDirect Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design - ScienceDirect](https://ars.els-cdn.com/content/image/1-s2.0-S0141933117302090-gr1.jpg)